There is an increasing demand for data storage devices to be constructed which are smaller and consume less power than their predecessor designs, whilst retaining high performance. New technologies are being developed which allow a reduction in size of the individual transistors making up each storage cell. However, as the storage cells decrease in size, the variation in behaviour between individual storage cells tends to increase, and this can adversely affect predictability of operation. This variation in operation of the individual storage cells can give rise to significant failure rates when trying to run the storage devices at high speed to meet the performance requirements. It is often also the case that there is a desire to use a lower power supply voltage for the storage device in order to reduce power consumption, but this can further increase the likelihood of failed operation within individual storage cells. Accordingly, in modern technologies, it is becoming more and more difficult to produce data storage devices such as memory devices where the individual cells have the required stability to ensure effective retention of data (stability sometimes being measured in terms of static noise margin (SNM)), whilst also having required write-ability (WM) to ensure that new data values can be stored in the cells within the time period allowed for a write operation.
Faced with these issues, various assistance mechanisms have been developed which seek to assist individual memory cells in operating correctly when write and read operations are performed on those cells. For example, the article “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply” by K Zhang et al, Intel, published in ISSCC 2005, Session 26, describes a six transistor SRAM cell (often referred to as a 6T SRAM cell) which is stable in all conditions, but requires write assist (WA) circuitry to improve the likelihood of individual cells operating correctly when written to. The write assist circuitry disclosed in this article is illustrated schematically in FIG. 1, and is based on the idea of lowering the supply voltage to an addressed memory cell just prior to the write operation, the lower supply voltage lowering the stability of the memory cell, and therefore making it more easy to write into.
FIG. 1 shows an array of memory cells 240, 242, 244, 246, 248, 250, 252, 254 provided in association with a particular column multiplexer 260 of the memory array. Each row is addressed by a word line 200, 202, and each column has a power supply voltage provided by a supply voltage line 230, 232, 234, 236. As is known in the art, each of the columns also has a pair of bit lines 210, 212, 214, 216, 218, 220, 222, 224 associated therewith. From an address provided to the memory device, a row and column within the memory device is identified, with the addressed memory cell being the memory cell at the intersection between the identified row and column. For a read operation, the word line 200, 202 associated with the selected row is selected in order to enable a row of cells, and then the column multiplexer 260 outputs to the sense amplifier 270 an indication of the voltages on the pair of bit lines associated with the selected column to allow the sense amplifier to detect the value stored in the addressed memory cell. For a write operation, the word line is enabled in the same manner, and the voltage on one of the pair of bit lines associated with the selected column is then discharged to identify the data value to be stored in the addressed memory cell. In this design multiplexers are provided which can select between a main supply voltage and a specially generated lower column supply voltage provided. Just prior to the write operation, the relevant multiplexer associated with the selected column is driven to select, as the voltage output on the supply voltage line for that column, the reduced column supply voltage.
A problem with the above design is that it requires a dedicated voltage generator to produce the extra reduced column supply, and this either needs to be accommodated within the design of the memory device, or else be provided externally, with additional metal lines being provided to route the voltage supply from that voltage generator. For any change in height or width of the memory device, the capacitances observed on the various column supply voltage lines will change, and this will typically require a redesign or tuning of the voltage generator used to generate the extra column supply voltage, to ensure that the voltage on the column supply voltage line can be reduced sufficiently quickly in the short period of time allowed before the write occurs to the addressed memory cell. Such voltage generators will also be susceptible to temperature and voltage variations, which may require correcting circuits to be added.
In addition to these problems, in memory devices designed for low power applications, the presence of the additional voltage generator leads to significant power consumption since the additional voltage supply must be maintained at all times to enable that supply voltage to be available ahead of any write operation.
Other types of storage cells that also have difficulty switching state are standard latch cells comprising inverters arranged in a feedback loop. FIG. 2 shows an example of such a cell of the prior art, this cell comprising a device for allowing the latch to be consistently written to. This device comprises transistors 310 and 320 which receive the same clock signal as the transmission gate 340, thus when the transmission gate is enabled and the storage latch is open and can receive a value, the inverter 330 is powered down, such that a value can be written to the feedback loop. When the transmission gate is closed, the inverter 330 is powered and the feedback loop stores the value. A disadvantage of this mechanism is that it adds two additional transistors for each storage cell.
It would be desirable to be able to provide a mechanism for enabling a storage cell to be written to consistently without adding too much additional circuitry and without unduly affecting the stability of other neighbouring storage cells.